Analysis of integrated circuit (IC) components, and understanding the results following electrostatic discharge (ESD) stress testing, is often cumbersome, as it involves the interpretation of a large amount of data. This is especially the case for devices with large number of pins, with each pin typically being tested at different stress levels. Engineers often spend considerable amounts of time sifting through this large amount of data, yet have no available efficient analysis tools to obtain an accurate picture of the overall results.
For example, various methods for testing both ESD and latchup performance are used to characterize the operation and reliability of devices. However, the analysis of those test results is difficult due to the volume of data and the inability to identify specific failure thresholds which are often defined in terms of some conditions a device must withstand for reliability assurance. During preliminary ESD tests, the IC pin voltage versus current (often known or referred to as IV) curves are analyzed for leakage degradation to measure their response after ESD stress and analyze the chips ability to withstand the ESD stress. The ESD tests may include human body model (HBM), machine model (MM), or charged device model (CDM) tests. Similarly, the latchup method includes measuring the tolerable current injection level for input/output (IO) pins of a chip before a latchup event occurs in the device. Other reliability test methods, such as those that measure high temperature operating life (HTOL), operational voltage range tests (VDDmin, VDDmax), channel hot carrier (CHC), negative bias temperature instability (NBTI), highly accelerated stress test (HAST), biased HAST (BHAST), early life failure rate (ELFR), or the like may be used to characterize the operation and reliability of devices. Many of these involve statistical distribution analyses.